Chip stacking technology can allow two chips to be arranged more closely together, thereby enabling faster data transmission between the two chips and consuming less power. Memory chips can be stacked together to obtain a memory module with a large storage capacity. In addition to stacking two identical chips, two chips with different functions may also be stacked together to create a combination offering multiple functions.
In a memory chip stack, each memory chip has a chip selection (CS) terminal, which is used to enable the memory chip. For example, a DRAM chip can have a row address strobe (RAS), a column address strobe (CAS), or a chip selection pin (CSP) as a chip selection terminal. When a signal is applied to the chip selection terminal of a chip in a memory chip stack, the chip can be accessed, while other chips in the stack cannot be accessed.
Conventionally, signals applied to the chip selection terminals of the memory chip stack will flow through wires. Such wires require additional processes to form, with increasing risk of signal trace shortage when producing increasingly finely-pitched products. Moreover, long wires cause signal delays by occupying more space, and result in greater chip package size.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.